AXI (“Advanced eXtensible Interface”) is part of the AMBA specification defined by ARM and is used as a central bus in FPGA and SoC systems.

Typical application areas:

• Interfacing ARM processor systems with FPGA logic
• Integration of PCIe IP cores
• Interconnection of internal FPGA components and IP cores

We have developed both an AXI-Lite slave and an AXI master to connect custom logic to existing systems.

Our AXI master supports different bus widths and enables flexible adaptation to various data paths through barrel shifting.

These modules are used in AMD/Xilinx, Intel SoC, and FPGA systems.

PCIe (“Peripheral Component Interconnect Express”) is a high-speed standard for connecting external components to processor systems.

We have experience with both legacy PCI and modern PCIe.

Our work includes:

• Hardware design
• FPGA design
• Linux driver development

Application areas:

• PC expansion cards
• Integration of external PCIe components into embedded systems (e.g., NXP i.MX8)
• Use of PCI in embedded systems, e.g., based on the TQM5200B

We have used PCI/PCIe in both PC-based systems and embedded platforms, implementing complete data transfer including DMA, memory mapping, and interrupt handling.

UART (“Universal Asynchronous Receiver/Transmitter”) is a simple serial interface that is available in nearly every microcontroller.

We use UART in various applications:

• Interfacing microcontrollers and FPGAs with SoMs
• Debug and diagnostic interface in embedded systems
• Linux console for embedded platforms
• Connecting embedded systems to PC systems via UART-to-USB bridges
• Communication between embedded systems via RS-422
• Configuration interfaces via RS-232
• Use of RS-232 Bluetooth adapters for wireless connections

We achieve data rates of up to 3 MBd.

SPI (“Serial Peripheral Interface”) is a serial interface used to connect peripherals to microcontrollers, SoCs, and FPGAs.

We use SPI and Quad SPI (QSPI) in various applications:

• Interfacing external components with microcontrollers and SoCs
• Communication between FPGA and peripherals
• Extending SoMs with additional functions and peripherals
• Accessing flash memory and other SPI-based devices

Achievable data rates range from a few kilohertz up to several hundred megahertz, for example when interfacing with SD cards.

For FPGA systems, we develop SPI modules in VHDL, tailored to the required SPI mode, data width, and specific application requirements.

Due to the clear structure of the interface, such customized modules can be implemented efficiently. In many cases, the development effort for a lean, application-specific module is lower than integrating and adapting a universal, generic SPI subsystem.

In total, we have implemented around 30 SPI solutions for various projects and customers.

SDRAM (“Synchronous Dynamic Random-Access Memory”) is a clocked main memory that is connected to a processor system or FPGA via a memory controller.

We have used SDRAM in various FPGA systems, particularly in the form of DDR3 and DDR4 memory.

The interfaces were implemented using the respective controller IPs:

• AMD/Xilinx MIG
• Intel EMIF

Memory access was performed both directly from FPGA logic and, in SoC systems, via AXI masters and DMA.

The goal was always to achieve the maximum possible bidirectional data throughput.

Ethernet is the leading standard for data communication in local area networks.

We use Ethernet in a wide range of embedded systems and FPGA designs.

Our work includes:

• Hardware design for Ethernet-based systems
• Integration of Ethernet via PCIe/Ethernet bridges
• Use of Power over Ethernet (PoE) to supply external devices

A key focus is the integration of Ethernet in FPGA SoC systems:

• Interfacing 4 × 10G and 16 × 1G Ethernet ports between FPGA logic and SoC processors
• Implementation of high-performance data paths between FPGA, AXI, and DMA
• Development of Linux Ethernet drivers for these interfaces
• Integration up to Linux user space

In addition, we have implemented Ethernet directly in FPGA logic:

• 1G and 10G Ethernet designs in FPGA
• Generation and processing of UDP packets in FPGA logic
• Implementation of a simple Ethernet switch with packet filtering in an FPGA SoC
• Dynamic switching between MAC, FPGA logic, and processor system

For verification and long-term stability, we perform extensive testing:

• In TCP/IP-based systems, we use tools such as iperf3 for load and stability testing
• In FPGA designs, we implement internal tests by looping back the TX path to the RX path, which is particularly efficient with fiber optic connections
• Evaluation of packet counts and checksums to ensure data integrity

Power over Ethernet (PoE) enables the transmission of data and electrical power over a single Ethernet cable.

We have used PoE in an embedded system to supply power to an operator panel.

For this purpose, a PSE system was developed to provide power to external devices via Ethernet.

The implementation supports the IEEE 802.3af and IEEE 802.3at standards. Support for IEEE 802.3bt was considered during development and can be added as an upgrade.

The required 48 V supply voltage was generated from an existing 24 V supply using a DC/DC boost converter.

For verification and environmental testing, we developed a PoE load setup, which was used in particular for testing in a climate chamber.

The integration included the selection and implementation of suitable PoE controllers, as well as the design of the power supply and protection circuitry.

A framebuffer is used to store image data for output to a display.

We have used framebuffers in FPGA systems to drive VGA and DisplayPort interfaces.

The image data is stored in SDRAM and transferred to the display via continuous data streams from the FPGA logic.

For integration into embedded systems, we developed a framebuffer driver for Linux to enable display output interfacing with the operating system.

Modern FPGAs feature integrated gigabit transceivers that are used for high-speed interfaces.

We have experience using them in various systems, including:

• Ethernet, PCIe, and DisplayPort

Depending on the application, integration is carried out either via corresponding IP cores (e.g., Ethernet MAC or DisplayPort core) or through direct use of the transceivers.

For example, we have implemented direct use of gigabit transceivers in a fiber optic extender, where both link control and channel coding were developed in-house.

The transceivers are interfaced at the PMA (Physical Medium Attachment) and PCS (Physical Coding Sublayer) levels via the corresponding IP cores.

VGA is an analog video interface used to drive displays.

We have used VGA in FPGA systems for image output, for example in simple operator interface and visualization applications.

The video signals are generated directly in the FPGA logic, including the required timing signals for synchronization and image generation.